1. Field of the Invention
The present invention generally relates to the formation of trenches in semiconductor substrates and, more particularly, to the formation of trench capacitors with a buried plate at extremely high integration densities.
2. Description of the Prior Art
High processing speed in currently available data processors must be supported by large amounts of high speed random access memory. Due to reduced device counts per memory cell, much of the required storage is provided by dynamic random access memories (DRAMs) so that a much greater number of memory cells can be provided on a single chip. In such devices, the density at which memory cells, principally comprising one storage capacitor per memory cell, is of great importance since the capacitance of each capacitor is very limited due to small size while that capacitance must be comparable to the capacitance of the word line and bit line to achieve adequate operating margins for the sense amplifiers used to detect the presence or absence of stored charge. Therefore, the trenches must be formed to relatively large depths while being very closely spaced. The same geometries are also important for other trench structures such as isolation trenches.
In recent years, it has also been the practice to provide a buried plate within the semiconductor substrate in which the trench capacitors are formed. A buried plate provides the capability of controlling the voltage on one plate of each of a plurality of capacitors rather than controlling the voltage on the substrate; the latter typically requiring relatively increased current. Altering the voltage on a plate of a plurality of capacitors during read or write operations can advantageously be used to increase operating margins. Further, as memory capacities have increased, it is often desirable to partition the memory by partitioning of the buried plate and the partitioning of the buried plate further reduces the current required to alter the voltage thereon. Independent control of voltage of the buried plate and the substrate also avoids interference or operational trade-offs between the capacitors of the memory and transistors in sense amplifiers and addressing circuits also formed on the substrate. Perhaps most importantly, however, the use of a buried plate allows limitation of the voltage across the capacitor dielectric to V.sub.dd /2, potentially allowing reduction of trench depth and/or the use of a thinner capacitor dielectric layer.
While formation of a buried plate can be achieved by formation of a layer of doped polysilicon in the substrate prior to trench formation, the capacitance (and uniformity of capacitance) of the storage nodes is dependent on the positioning of capacitor plates across the capacitor dielectric. The coincidence of positioning can be most reliably achieved by the provision of a diffusion source in the trenches. This, in turn, has required etching to a depth above the capacitor plates (where no dopant diffusion is to occur) followed by a series of complex deposition steps to form diffusion barriers and isolation structures such as isolation collars. Then, a further etch to a depth corresponding to the capacitor plate dimensions was required followed by partial filling of the trenches with a doped material (e.g. silicon) to determine the depth or height of the capacitor within the trench and to function as a diffusion source. These processes were, in turn, followed by filling the remainder of the trench with an undoped or lightly doped semiconductor which functions as a diffusion barrier during manufacture and, later, as a contact.
However, in this multi-step process, referred to hereinafter as a two-step trench (although, in practice, a plurality of costly etch, deposition and etch back sequences are generally employed; the depth of the second etch corresponding to the capacitor plate dimensions being particularly difficult to control or perform repeatably), the highly doped material (e.g. polysilicon) has a tendency to oxidize, forming an insulating layer at the interface to the undoped or lightly doped material (either before or after the deposition of the undoped or lightly doped material) and can interrupt continuity to the capacitor plate serving as the storage node. Such interruption of continuity will not become evident until the memory array is substantially otherwise complete; reducing not only manufacturing yield but increasing the cost of chips which will ultimately be found defective and unusable.
Further, the two-step trench process inherently causes problems associated with step corners and barrier collar erosion. Step corners, formed by etching of the substrate or p-well laterally under the diffusion barrier or isolation collar often cause voids or crystal lattice dislocations, leading to capacitor leakage, while barrier collar erosion, caused by repeated deposition and etch back during formation of the highly doped diffusion source and the formation of a diffusion barrier thereover to prevent dopant diffusion in the upper regions of the trench, leads to a thinner and potentially irregular isolation collar with consequent reduction of the voltage which may be applied to the capacitor without breakdown.
Further in regard to step corner formation, while some lateral etching occurs laterally under the isolation collar, the isolation collar also restricts the etching process somewhat and reduces the transverse dimension of the lower portion of the trench; reducing the potential capacitance of the resulting capacitor for a given integration density and capacitor "footprint" (e.g. maximum transverse dimension of the trench). Additionally, regulation of depth of fill of the highly doped material is difficult when performed by deposition and etch back both from the standpoint of filling a very narrow trench and the fact that etching rates within a trench of sub-micron transverse dimension is highly dependent on trench dimensions, generally resulting in poor capacitance uniformity on a chip, across a wafer or from wafer to wafer. Nevertheless, prior to the present invention, the two-step trench structure has remained the methodology of choice for formation of trench capacitors having a buried plate at high integration densities.